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APPROVED PRODUCT
SM560
Spread Spectrum Clock Generator Features
* * * * * * * * 25 to 108 MHz Operating Frequency Range Wide (9) Range of Spread Selections Accepts Clock and Crystal Inputs Low Power Dissipation
3.3V = 85 mw. (50 MHz)
Applications
* * * VGA Controllers LCD Panels and Monitors Printers and Multi-Function devices (MFP).
Frequency Spread Disable Function Center Spread Modulation Low Cycle-to Cycle Jitter 8-pin SOIC package
Benefits
* * * Peak EMI reduction by 8 to 16dB Fast Time to Market Cost Reduction
General Description
The Cypress SM560 is a Spread Spectrum Clock Generator (SSCG) IC used for the purpose of reducing Electro Magnetic Interference (EMI) found in today's high-speed digital electronic systems. The SM560 uses a Cypress proprietary Phase-Locked Loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and frequency modulate the input frequency of the reference clock. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies of Clock (SSCLK1) is greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory requirements and time to market without degrading the system performance. The SM560 is a very simple and versatile device to use. The frequency and spread % range is selected by programming S0 and S1digital inputs. These inputs use three (3) logic states including High (H), Low (L) and Middle (M) logic levels to select one of the 9 available Frequency Modulation and Spread % ranges. Refer to Tables 2 and 3 for programming details. The SM560 is optimized for SVGA (40 MHz) and XVGA (65MHz) Controller clocks and also suitable for the applications with the frequency range of 25 to 108 MHz. A wide range of digitally selectable spread percentages is made possible by using Three-Level (High, Low and Middle) logic at the S0 and S1 digital control inputs. The output spread (frequency modulation) is symmetrically centered on the input frequency. Spread Spectrum Clock Control (SSCC) function enables or disables the frequency spread and is provided for easy comparison of system performance during EMI testing. The SM560 is available in an 8-pin SOIC package with a 0 to 70C operating temperature range.
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07020 Rev. **
05/04/2001 Page 1 of 10
APPROVED PRODUCT
SM560
Spread Spectrum Clock Generator Block Diagram
250 K
Xin/ CLK
1 4 pf
REFERENCE DIVIDER PD CP LF
MODULATION CONTROL
Xout
8 8 pF FEEDBACK DIVIDER VCO
VDD VSS
2 INPUT DECODER LOGIC DIVIDER AND MUX
3
4
SSCLK
5
6
7
SSCC
S1
S0
Figure 1. Block Diagram
Ordering Information
Operating Temperature Range 0 to 70C
Part No. SM560BZ
Package 8 Pin SOIC
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07020 Rev. **
05/04/2001 Page 2 of 10
APPROVED PRODUCT
SM560
Spread Spectrum Clock Generator Pin Configuration
Xin/CLK VDD VSS SSCLK 1 2 3 4 8 7 6 5 Xout S0 S1 SSCC
Figure 2. Pin Configuration
Pin Description
Pin # 1 Symbol Xin/CLK Type I Description Clock or Crystal connection input. Refer to the Table-2 and 3 for input frequency range selection. 2 3 4 5 VDD GND SSCLK SSCC P P O I Positive power supply. Power supply ground. Modulated clock output. Spread Spectrum Clock Control (Enable/Disable) function. SSCG function is enabled when input is high and disabled when input is low. This pin is pulled high internally. 6 S1 I Tri-Level Logic input control pin used to select Frequency and Bandwidth. Frequency/Bandwidth selection and Tri-Level Logic programming details can be found on page 4. 7 S0 I Tri-Level Logic input control pin used to select Frequency and Bandwidth. Frequency/Bandwidth selection and Tri-Level Logic programming details can be found on page 4. 8 Xout O Oscillator output pin connected to crystal. Leave this pin unconnected If an external clock drives Xin/CLK.
Table 1. Pin Description
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07020 Rev. **
05/04/2001 Page 3 of 10
APPROVED PRODUCT
SM560
Spread Spectrum Clock Generator Frequency and Spread % Selection (Center Spread)
25 - 54 MHz (Low Range) Input Frequency (MHz) 25 - 35 35 - 40 40 - 45 45 - 50 50 - 54 S1=M S0=M (%) 3.8 3.5 3.2 3.0 2.8 S1=M S0=0 (%) 3.2 3.0 2.8 2.6 2.4 S1=1 S0=0 (%) 2.8 2.5 2.4 2.2 2.0 S1=0 S0=0 (%) 2.3 2.1 1.9 1.8 1.7 S1=0 S0=M (%) 1.9 1.7 1.6 1.5 1.4
Select the Frequency and Center Spread % desired and then set S1, S0 as indicated.
50 - 108 MHz (High Range) Input Frequency (MHz) 50 - 60 60 - 70 70 - 80 80 - 100 100 - 108 S1=1 S0=M (%) 2.5 2.4 2.3 2.0 1.8 S1=0 S0=1 (%) 1.9 1.8 1.6 1.4 1.3 S1=1 S0=1 (%) 1.2 1.1 1.1 1.0 0.8 S1=M S0=1 (%) 1.0 0.9 0.9 0.8 0.6
Select the Frequency and Center Spread % desired and then set S1, S0 as indicated.
Table 2. Frequency and Spread % Selection
Tri-Level Logic
With binary logic, 4 states can be programmed with 2 control lines where as Tri-Level Logic can program 9 logic states using 2 control lines. Tri-Level Logic in the SM560 is implemented by defining a third logic state in addition to the standard logic "1" and "0". Pin 6 and 7 of the SM560 recognize a logic state by the voltage applied to the respective pin. These states are defined as "0" (Low), "M" (Middle) and "1" (One). Each of these states have a defined voltage range that is interpreted by the SM560 as a "0", "M" or "1" logic state. Refer to table 5 for voltage ranges for each logic state. By using two equal value resistors (typically 20K) the "M" state can be easily programmed. Pins 6 or 7 can be tied directly to ground or VDD for Logic "0" or "1" respectively. See examples below; VDD = 3.3 VDC VDD = 3.3 VDC VDD = 3.3 VDC
SM560
20K
SM560
SM560
7
1.65 VDC
7
7
6
0 VDC
20K
6
6
5
5
5
EX. 1
EX. 2
EX. 3
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07020 Rev. **
05/04/2001 Page 4 of 10
APPROVED PRODUCT
SM560
Spread Spectrum Clock Generator
Absolute Maximum Ratings
Supply Voltage(AVDD or DVDD): +6V AVDD - DVDD: +/-300mV AGND - DGND: +/-300mV Junction Temperature (10-sec. soldering): +300C
Note: Operation at any Absolute Maximum Rating is not implied.
Operating Temperature: 0 to 70C Storage Temperature: -65 to +150C
DC Electrical Characteristics
Test Conditions: VDD=3.3V, Temp. =25C and CL (Pin 4) =15pF, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Conditions VDD Power Supply Range 2.97 3.3 3.63 V +/- 10 % VINH Input High Voltage 0.85VDD VDD VDD V S0 and S1 only. VINM Input Middle Voltage 0.40VDD 0.50VDD 0.60VDD V S0 and S1 only. VINL Input Low Voltage 0.0 0.0 0.15VDD V S0 and S1 only. VOH1 VOH2 VOL1 VOL2 Cin1 Cin2 Cin2 IDD1 IDD2 Output High Voltage Output High Voltage Output Low Voltage Output Low Voltage Input Capacitance Input Capacitance Input Capacitance Power Supply Current Power Supply Current 2.4 2.0 3 6 3 4 8 4 30 35 Table 5 0.4 1.2 5 10 5 40 45 V V V V pF pF pF ma ma IOH = 6 ma IOH = 20 ma IOH = 6 ma IOH = 20 ma Xin/CLK (Pin 1) Xout (Pin 8) S0, S1, SSCC (Pins 7,6,5) FIN = 40 MHz FIN = 65 MHz
Electrical Timing Characteristics
Test Conditions: VDD=3.3V, T=25C and CL=15pF, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit ICLKFR Input Clock Frequency Range 25 108 MHz Trise Clock Rise Time (Pin 4) 1.2 1.4 1.6 ns Tfall Clock Fall Time (Pin 4) 1.2 1.4 1.6 ns DTYin DTYout JCC Input Clock Duty Cycle Output Clock Duty Cycle Cycle-to-Cycle Jitter 20 45 50 50 125 Table 6 80 55 175 % % ps Conditions VDD = 3.30V SSCLK1 @ 0.4 - 2.4V SSCLK1 @ 0.4 - 2.4V XIN/CLK (Pin 1) SSCLK1 (Pin 4) Fin = 25 - 108 MHz
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07020 Rev. **
05/04/2001 Page 5 of 10
APPROVED PRODUCT
SM560
Spread Spectrum Clock Generator SSCG Theory of Operation
The SM560 is a Phase Lock Loop (PLL) type clock generator using a proprietary IMI design. By precisely controlling the bandwidth of the output clock, the SM560 becomes a Low EMI clock generator. The theory and detailed operation of the SM560 will be discussed in the following sections. EMI All digital clocks generate unwanted energy in their harmonics. Conventional digital clocks are square waves with a duty cycle that is very close to 50 %. Because of this 50/50-duty cycle, digital clocks generate most of their rd th th harmonic energy in the odd harmonics, i.e.; 3 , 5 , 7 etc. It is possible to reduce the amount of energy contained in the fundamental and odd harmonics by increasing the bandwidth of the fundamental clock frequency. Conventional digital clocks have a very high Q factor, which means that all of the energy at that frequency is concentrated in a very narrow bandwidth, consequently, higher energy peaks. Regulatory agencies test electronic equipment by the amount of peak energy radiated from the equipment. By reducing the peak energy at the fundamental and harmonic frequencies, the equipment under test is able to satisfy agency requirements for Electro-Magnetic Interference (EMI). Conventional methods of reducing EMI have been to use shielding, filtering, multi-layer PCB's etc. The SM560 uses the approach of reducing the peak energy in the clock by increasing the clock bandwidth, and lowering the Q. SSCG SSCG uses a patented technology of modulating the clock over a very narrow bandwidth and controlled rate of change, both peak and cycle to cycle. The SM560 takes a narrow band digital reference clock in the range of 25 108 MHz and produces a clock that sweeps between a controlled start and stop frequency and precise rate of change. To understand what happens to a clock when SSCG is applied, consider a 65 MHz clock with a 50 % duty cycle. From a 65 MHz clock we know the following; Clock Frequency = fc = 65 MHz. Clock Period = Tc = 1/65 MHz = 15.4 ns.
50 %
50 %
Tc = 15.4 ns
If this clock is applied to the Xin/CLK pin of the SM560, the output clock at pin 4 (SSCLK) will be sweeping back and forth between two frequencies. These two frequencies, F1 and F2, are used to calculate to total amount of spread or bandwidth applied to the reference clock at pin 1. As the clock is making the transition from f1 to f2, the amount of time and sweep waveform play a very important role in the amount of EMI reduction realized from an SSCG clock. The modulation domain analyzer is used to visualize the sweep waveform and sweep period. Figure 3 shows the modulation profile of a 65 MHz SSCG clock. Notice that the actual sweep waveform is not a simple sine or sawtooth waveform. Figure 4 is a scan of the same SSCG clock using a spectrum analyzer. In this scan you can see a 6.48 dB reduction in the peak RF energy when using the SSCG clock.
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07020 Rev. **
05/04/2001 Page 6 of 10
APPROVED PRODUCT
SM560
Spread Spectrum Clock Generator
Modulation Rate Spectrum Spread Clock Generators utilize frequency modulation (FM) to distribute energy over a specific band of frequencies. The maximum frequency of the clock (Fmax) and minimum frequency of the clock (Fmin) determine this band of frequencies. The time required to transition from Fmin to Fmax and back to Fmin is the period of the Modulation Rate, Tmr. Modulation Rates of SSCG clocks are generally referred to in terms of frequency or Fmod = 1/Tmod. The input clock frequency, Fin, and the internal divider count, Cdiv, determine the Modulation Rate. In some SSCG clock generators, the selected range determines the internal divider count. In other SSCG clocks, the internal divider count is fixed over the operating range of the part. The SM560 and SM561 have a fixed divider count, as listed below; Device SM560 SM561 Cdiv 1166 2332
(All Ranges) (All Ranges)
Example: Device = Fin = Range =
SM560 65 MHz S1 = 1, S0 = M
Then; Modulation Rate = Fmod = 65 MHz/1166 = 55.8 kHz.
-6.58 dB
BW = 2.46% Modulation Profile Spectrum Analyzer
Figure 3. SSCG Clock, SM560, Fin = 65 MHz
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07020 Rev. **
05/04/2001 Page 7 of 10
APPROVED PRODUCT
SM560
Spread Spectrum Clock Generator
SM560 Application Schematic
3.3 uH.
L1
NOTE 1.
C2
Y1
C3
27 pF
40 MHz
27 pF C4 .01 uF.
VDD
1 VDD 2
Xin/CLK
Xout
8
R2 20 K
VDD
S0
7
C5 22 uF.
C6 0.1 uF 3 GND S1 6
R4 20 K
R5 4 Application Load 22 SM560 SSCLK SSCC 5 VDD
Figure 4. Application Schematic The schematic in figure 2 above demonstrates how the SM560 is configured in a typical application. This rd application is using a 40 MHz reference derived from a 3 overtone crystal connected to pins 1 and 8. Since Y1 rd is a 3 overtone crystal a notch filter is created with L1 and C3 to dampen the gain of the oscillator at the fundamental frequency of this crystal which is 13.33 MHz. Figure 2 also demonstrates how to properly use the tri-level logic employed in the SM560. Notice that resistors R2 and R4 create a voltage divider that places VDD/2 on pin 7 to satisfy the voltage requirement for an "M" state. With this configuration, the SM560 will produce an SSCG clock that is at a center frequency of 40 MHz. Referring to table 2, range "0, M" at 40 MHz will generate a modulation profile that has a 1.7 % peak to peak spread. Note 1: The value of L1 is calculated such that L1 and C3 are tuned to a frequency that is 130% higher than the fundamental frequency of the crystal.
ZC1 = 1/2fC ZC1 = 1/6.28 (17.33 MHz) (27 pF) ZC1 = 340 ZL1 = 2FL L = ZL1/2f L = 340/6.28(17.33 MHz) L = 3.12 uH
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07020 Rev. **
05/04/2001 Page 8 of 10
APPROVED PRODUCT
SM560
Spread Spectrum Clock Generator
8 PIN SOIC Packing Drawing
8 Pin SOIC Outline Dimensions
INCHES SYMBOL A C L A1 A2 B MIN 0.053 0.004 0.047 0.013 0.007 0.189 0.150 NOM 0.050 BSC 0.228 0.016 0 0.244 0.050 8 5.80 0.40 0 MAX 0.069 0.010 0.059 0.020 0.010 0.197 0.157 MIN 1.35 0.10 1.20 0.33 0.19 4.80 3.80 MILLIMETERS NOM 1.27 BSC 6.20 1.27 8 MAX 1.75 0.25 1.50 0.51 0.25 5.00 4.00
E
H
C D E
D A2 A1 B e A
a
e H L a
Notes:
NOTICE
Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design, performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. Products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corporation for the use of its products in the life supporting and medical applications.
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07020 Rev. **
05/04/2001 Page 9 of 10
APPROVED PRODUCT
SM560
Spread Spectrum Clock Generator
Document Title: SM560 Spread Spectrum Clock Generator Document Number: 38-07020
Rev. **
ECN No. 106948
Issue Date 06/07/01
Orig. of Change IKA
Description of Change Convert from IMI to Cypress
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07020 Rev. **
05/04/2001 Page 10 of 10

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